This application claims priority to Korean Patent Application No. 570/1999, filed on Jan. 12, 1999, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a dual gate of a semiconductor device, which simplifies process steps and improves reliability of the semiconductor device.
2. Background of the Related Art
Generally, in fabrication of MOS devices, a single poly gate structure requires a buried PMOS transistor, which increases a short channel effect. In this case, it is difficult to fabricate a device having a gate length of 0.25 xcexcm or less. A dual gate structure has been proposed, in which a P-poly gate is used in a PMOS transistor and an N-poly gate is used in an NMOS transistor. FIGS. 1A to 1F show cross-sectional views iliustrating a related art method for forming a dual gate of a semiconductor device.
As shown in FIG. 1A, an isolation region 12 is partially formed in a semiconductor substrate 11 by a local oxidation of silicon (LOCOS) process or a trench isolation process. Thereafter, a P well region 13 and an N well region 14 are selectively formed in the semiconductor substrate 11 by impurity ion implantation.
The N well region 14 is masked during the formation of the P well region 13, while the P well region 13 is masked during formation of the N well region 14. (These steps are not illustrated in the figures).
As shown in FIG. 1B, a gate insulating film 15 is formed on the semiconductor substrate 11. Subsequently, an undoped polysilicon layer 16 is deposited on the gate insulating film 15. A first photoresist 17 is then selectively deposited on the polysilicon layer 16. The first photoresist 17 is then patterned by exposure and developing processes to mask the polysilicon layer 16 of the N well region 14. N-type impurity ions are then implanted into the exposed polysilicon layer 16 of the P well region 13.
As shown in FIG. 1C, the first photoresist 17 is removed and then a second photoresist 17a is deposited on an entire surface of the semiconductor substrate including the polysilicon layer 16, into which the N-type impurity ions were implanted. The second photoresist 17a is patterned by an exposure and developing processes to mask the polysilicon layer 16 (into which the N-type impurity ions are implanted) of the P well region 13. P-type impurity ions are implanted into the exposed polysilicon layer 16. The P-type the impurity ion implantation may also be performed prior to the N-type impurity ion implantation.
As shown in FIG. 1D, the second photoresist 17a is removed, and a tungsten silicide (WSi2) or a tungsten (W) layer 18 is formed on the polysilicon layer 16. Subsequently, a third photoresist is deposited on the tungsten suicide layer 18. The third photoresist is patterned by exposure and developing processes to form a photoresist pattern 19. As shown in FIG. 1D, the photoresist pattern 19 is formed on the tungsten silicide layer 18.
As shown in FIG. 1E, the tungsten silicide layer 18, the polysilicon layer 16, and the gate insulating film 15 are selectively removed by an etching process using the photoresist pattern 19 as a mask, to form a first gate electrode 20 and a second gate electrode 20a. The first gate electrode 20 is for an NMOS transistor and the second gate electrode 20a is for a PMOS transistor.
As shown in FIG. 1F, an oxide film or a nitride film is deposited on the entire surface of the semiconductor substrate including the gate electrodes 20 and 20a, and then etched back to form sidewall spacers 21 at both sides of the gate electrodes 20 and 20a. 
Thereafter, the N well region 14 is masked, and then impurity ions are implanted into the P well region 13 at both sides of the first gate electrode 20 to form first source/drain impurity ion diffused regions 22.
Subsequently, the P well region 13 is masked, and then impurity ions are implanted into the N well region 14 at both sides of the second gate electrode 20a to form second source/drain impurity ion diffused regions 22a. 
The second source/drain impurity ion diffused region 22a may also be formed Prior to the first source/drain impurity ion diffused region 22.
The related art method for forming a dual gate of a semiconductor device has several problems.
First, ion implantation is performed twice in order to dope impurity ions into the undoped polysilicon layer 16. Also, ion implantation is performed twice when forming source/drain impurity ion diffused regions 22, 22a corresponding to each of the transistors. This complicates process steps and increases the number of masks, thereby increasing cost.
Second, during ion implantation into the polysilicon layer 16, the impurity ions pass through the polysilicon layer 16 if the polysilicon layer 16 is thin. This damages the gate insulating film 15, thereby deteriorating its insulating characteristics.
Moreover, during boron ion implantation when forming a gate electrode for the PMOS transistor, the boron ions act to vary the threshold voltage of the device because its fast diffusion speed affects a channel region of the FET.
Third, since the tungsten silicide layer 18 formed on the polysilicon layer 16 has resistivity of about 100 xcexcxcexa9cm, it is impossible to reduce sheet resistance to 10 xcexa9/sq or less, even though the polysilicon layer 16 is deposited to a thickness at 1000 xc3x85 or more.
Fourth, if a tungsten layer having resistivity lower than that of the tungsten silicide layer 18 is deposited on the polysilicon layer 16 to reduce resistance, titanium nitride (TiN) film or WN (tungsten nitride) film must additionally be formed to avoid reaction with silicon. This complicates process steps.
Fifth, a reoxidation process is required to restore damage caused to the gate insulating film 15 during the etching process for the formation of the gate electrode. However, selective reoxidation is required because the tungsten is likely to react with ambient O2. Therefore, selective oxidation should exactly satisfy possible oxidation conditions, such as a ratio of H2/O2, and oxidation temperature. In this case, there is a problem in that redundancy of the selective oxidation is low.
Finally, if a cell region and a logic region are formed in a single chip, the logic region requires a salicide process so that the logic region has a gate electrode material different from that of the cell region.
Accordingly, the present invention is directed to a method for forming a dual gate of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a dual gate of a semiconductor device, which improves reliability of the device and simplifies process steps by forming the same gate electrode material in both a cell region and a logic region.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in accordance with a first aspect of the present invention there is provided a method for forming a dual gate of a semiconductor device including the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and second gate patterns that include the semiconductor layer and the low resistance metal layer on the substrate corresponding to the first and second wells, forming sidewall spacers at sides of the first and second gate patterns, and exposing the first well and the first gate pattern, implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern to form a first source and a first drain, exposing the second well and the second gate pattern, implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern to form a second source and a second drain, and diffusing the impurity ions from the low resistance metal layer into the semiconductor layer to form first and second gate electrodes.
In another aspect of the present invention, there is provided a method for forming a dual gate of a semiconductor device, including the steps of selectively forming an isolation region on a semiconductor substrate, forming a P well region and an N well region in the semiconductor substrate, sequentially forming a gate insulating film, an undoped polysilicon layer, and a cobalt silicide layer on an entire surface of the semiconductor substrate, forming first and second gate patterns from the undoped polysilicon layer and the cobalt silicide layer on the substrate at the P well region and the N well region, respectively, forming sidewall spacers at sides of each of the first and second gate patterns and exposing the P well region including the first gate pattern, implanting N-type impurity ions into an upper portion of the first gate pattern and the P well region to form a first source and a first drain, exposing the N well region and the second gate pattern, implanting P-type impurity ions into an upper portion of the second gate pattern and the N well region to form a second source and a second drain, and doping the undoped polysilicon layer of the first and second gate patterns by diffusing the P-type and N-type impurity ions implanted into upper portions of the respective gate patterns to form first and second gate electrodes each including the cobalt silicide layer and the doped polysilicon layer, and at the same time forming source and drain impurity regions in the semiconductor substrate at both sides of the respective gate electrodes.
In another aspect of the present invention, in forming a gate electrode of embedded DRAM in which DRAM and a logic circuit are on a single chip, there is provided a method for forming a dual gate of a semiconductor device including the steps of dividing a semiconductor substrate into a DRAM region and a logic circuit region, and forming a P well region and an N well region in the DRAM region, sequentially forming a gate insulating film, an undoped polysilicon layer, and a low resistance metal layer on the semiconductor substrate, forming first and second gate patterns in the DRAM region and a third gate pattern in the logic circuit region by etching, forming sidewall spacers at sides of each of the first, second and third gate patterns, masking the N well region and second gate electrode pattern, implanting N-type impurity ions into a surface of the semiconductor substrate, exposing the N well region and second gate electrode pattern and then implanting P-type impurity ions into the surface of the semiconductor substrate, doping the undoped polysilicon layer of the first, second and third gate patterns by impurity ion diffusion, and at the same time forming source and drain impurity regions in the semiconductor substrate at sides of the gate patterns, and masking the DRAM region, and forming a second metal layer of the same material as the low resistance metal layer over the third gate pattern and on the substrate at sides of the third gate pattern.
In another aspect of the present invention, there is provided a method for forming a dual gate of a semiconductor device including the steps of forming a gate insulating film on a substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming a semiconductor layer on the gate insulating film, forming a metal layer on the semiconductor layer, partially removing the gate insulating film, the semiconductor layer and the metal layer to form first and second gate patterns over the first and second wells, respectively, forming sidewall spacers at sides of the first and second gate patterns, exposing the first well and the first gate pattern, forming a first source and a first drain by implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern, exposing the second well and the second gate pattern, forming a second source and a second drain by implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern, and diffusing the impurity ions from the metal layer into the semiconductor layer to form first and second gate electrodes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.